In this section, we will discuss adders which are circuit elements that perform the addition operation in binary arithmetic. The first circuit element that we’ll examine is the half-adder, which is shown in Figure 7.5.1.
A half-adder chip component takes two inputs \(A\) and \(B\) and produces two outputs: the sum \(S=A\oplus B\) and the carry \(C=A\cdot B\text{.}\) The half-adder truth table is given by Table 7.5.2.
This behavior characterizes binary addition, where \(S\) is the binary sum of \(A\) and \(B\text{.}\) In the event that \(A=1\) and \(B=1\text{,}\) we are forced to ‘carry’ a value of one over into the next highest bit using \(C=1\) because \(S\) cannot take the value of 2 in binary. In words, this means that \(A\) plus \(B\) equals \(S\) and we carry \(C\) to the next bit.
To handle addition for multi-bit numbers, our adder must be able to produce output values for \(S\) and \(C\) that account for any values ‘carried’ from the next lowest bit in addition to the values of \(A\) and \(B\) as demonstrated by the truth table in Table 7.5.3.
Table7.5.3.Full-adder truth table for the \(n\)th bit.
Here, \(A_n\text{,}\)\(B_n\text{,}\)\(S_n\text{,}\) and \(C_n\) are defined for the \(n\)th bit identically to the half-adder. The \(C_{n-1}\) input did not appear in the half-adder and represents the act of ‘carrying’ overflow values from the \((n-1)\)th bit to the \(n\)th bit. Table 7.5.3 is the truth table associated with the full-adder circuit element. The full-adder circuit element can be built using the logic gate arrangement in Figure 7.5.4.
The adders described above can be used to perform addition on multi-bit numbers, with one full-adder used for each bit. The addition of two 3-bit numbers
