So far, we’ve limited our treatment of digital circuits to those with outputs that are fully determined by input values at any given instant. In this section, we’ll study sequential logic, a branch of digial electronics in which circuit outputs depend on input values at that instant in addition to the history of input values. Though the ‘memory’ that we’ll observe in sequential logic circuits is rudimentary compared to that demonstrated by random access memory (RAM) and solid-state drives (SSDs) in computers, the circuits we’ll examine are the fundamental building blocks that make the more advanced applications possible.
The first sequential logic circuit element that we’ll examine is called a latch. Figure 7.6.1(a) shows the SR cross-NOR latch with inputs \(S\text{,}\)\(R\) and outputs \(Q\text{,}\)\(\overline{Q}\text{.}\)
The SR cross-NOR latch is designed such that \(Q=1\) when \(S=1\) and \(R=0\text{;}\) we’ll call this the ‘Set’ state. Likewise, the latch is designed so that \(Q=0\) when \(S=0\) and \(R=1\text{;}\) this is called the ‘Reset’ state. The output labeled \(\overline{Q}\) is in the state opposite to output \(Q\) in both of these cases, the desired result implied by the naming convention used for these outputs. Analysis of the internal NOR gates for these two input states requires that the outputs satisfy
In the Set state, \(S=1\) and \(R=0\text{.}\) Since \(S=1\text{,}\) the bottom NOR gate must produce \(\overline{Q}=0\) regardless of the value of \(Q\text{.}\) Then, since \(R=0\) and \(\overline{Q}=0\text{,}\) the top NOR gate produces \(Q=1\text{.}\) This is a self-consistent solution describing the latch behavior.
In the Reset state, \(S=0\) and \(R=1\text{.}\) Since \(R=1\text{,}\) the top NOR gate must produce \(Q=0\) regardless of the value of \(\overline{Q}\text{.}\) Then, since \(S=0\) and \(Q=0\text{,}\) the bottom NOR gate produces \(\overline{Q}=1\text{.}\) This is a self-consistent solution describing the latch behavior.
The third input state that we’ll consider is \(S=1\) and \(R=1\text{.}\) Just as for the two cases above, the output state for this case is fully determined by the input state values, resulting in \(Q=0\) and \(\overline{Q}=0\text{.}\) This state will be called the ‘Forbidden’ state and should be avoided in standard operation because the outputs are not inverses of each other as the naming convention indicates they should be.
The final input that we must examine is the case where \(S=0\) and \(R=0\text{.}\) Unlike the cases above, the feedback of output values to the NOR gate inputs must be considered. Combining (7.6.1) with \(S=R=0\) and Boolean Identity 11 (from List 7.2.1), we find that \(Q=\overline{\overline{Q_0}}=Q_0\) and \(\overline{Q} = \overline{Q_0}\) where the subscript zero represents the output states prior to entering the ‘Hold’ state. Though these look similar to identity statements, we must be careful in our interpretation. Logic gates take a finite amount of time to respond and update output values due to changes in input values. If we examine the NOR gate inputs at time \(t=t_0\) and assume a logic gate response time \(\delta t\text{,}\) our analysis would determine output values at \(t_1=t_0 + \delta t\text{.}\) Thus, when \(S(t_0)=0\) and \(R(t_0)=0\text{,}\) we find
The truth table in Table 7.6.4 collects our results for the SR cross-NOR latch from above. The behavior of this latch can alternatively be demonstrated in the timing diagram in Figure 7.6.5, showing the time response of the outputs based on input changes in time.
Figure7.6.5.Example timing diagram for the SR cross-NOR latch. Note that the final state has undetermined outputs. Outputs \(Q\) and \(\overline{Q}\) must be inverses of each other in this final state, but a race will determine which latch output reaches a HI state first with the other output renaming low. This unpredictability is the reason the ‘forbidden’ state should be avoided for our uses.
The SR cross-NAND latch shown in Figure 7.6.6 is a variation on the latch described above. In contrast to the previous latch, the SR cross-NAND latch tracks which input was most recently LO.
One application that makes use of the SR cross-NAND latch is the switch debouncer. When using a mechanical switch to turn current off and on through a load (as in Figure 7.6.7(a)), the connection at the instant of physical contact closing the switch can be be flaky and/or unstable, with the switch ‘bouncing’ back and forth between open and closed several times before a solid connection is made. The instability in the mechanical switch’s connection leads to the current rapidly oscillating between off and on through the load. This undesirable behavior is rectified through the use of a switch debouncer (as shown in Figure 7.6.7(b)). Connecting the switch to \(\overline{S}\) causes the latch inputs take values \(\overline{S}=0\) and \(\overline{R}=1\text{,}\) resulting in the latch Set state and allowing current to pass through the load. Likewise, when the switch is connected to \(\overline{R}\text{,}\) the latch enters the Reset state and no current flows through the load. During the switch transition between \(\overline{S}\) and \(\overline{R}\text{,}\) both \(\overline{S}=\overline{R}=+5\)V causing the switch to enter the Hold state. Therefore, any flakiness that may occur as the switch’s physical connection is made or broken does not result in any flakiness in the current through the load. Instead, the load current depends on the most recent connection only and maintains the output behavior even if the physical connection is unstable or flaky.
Figure7.6.7.A switch debouncer is used to reduce the ‘flakines’ of mechanical switches by entering the Hold state during the transition between switch positions.
There are latch applications where it may be beneficial to quickly enable or disable latch input control over the latch outputs. Figure 7.6.8 shows the circuit and truth table for a gated SR latch. When \(E=1\text{,}\) the latch is enabled meaning that the latch outputs are determined by the latch inputs. When \(E=0\text{,}\) the inputs are disabled and the latch enters the ‘Hold’ state independent of the values of \(S\) and \(R\text{.}\) The implementation of the gating functionality shown in Figure 7.6.8(a) results in a latch with active high inputs. This means that the latch, when enabled, has outputs that respond to inputs that are high. So, the Set state requires \(E=1\text{,}\)\(S=1\text{,}\) and \(R=0\text{.}\) This behavior is in contrast to the un-gated cross-NAND SR latch which has active low inputs.
All of the SR latch variants above suffer from the same issue, namely the accessibility of the state that we’ve labeled ‘forbidden’. It would be very beneficial to have a latch circuit for which the ‘forbidden’ state were inaccessible. We will examine two possible solutions to this problem that are each modifications to our original cross-NAND SR latch.
The JK latch uses feedback of the latch outputs back to the latch inputs to convert the ‘forbidden’ state (when both inputs are HI) into a ‘toggle’ state in which \(Q\) and \(\overline{Q}\) swap values. Figure 7.6.9 provides the circuit diagram and truth table for the JK latch.
While the JK latch uses feedback to repurpose the ‘forbidden’ state that appeared with SR latches, the D latch is designed instead to make it impossible to access that forbidden state at all. Figure 7.6.10 shows a modified SR latch version of the D latch with its truth table.
There are applications in which it is beneficial to place a latch into a specific state while overriding all gate and input states. Many latch circuits incorporate Preset and Clear inputs for just this purpose. The modified D latch circuit in Figure 7.6.11 provides an example of this functionality with active low Preset and Clear inputs.
