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Electronics A Guide for Physicists (DRAFT -- in development)

Derek J. Thuecks

Section 7.7 Flip-flops

In the last section, we discussed latches which are level-triggered circuits with output levels that depend on the input levels at any particular instant of time. Flip-flops, the topic for this section, are edge-triggered devices with output levels that change only at the instant at which a clock signal (CLK) transitions between high and low in a particular direction.
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Our first D flip-flop circuit design is shown in Figure 7.7.1 along with its circuit symbol and truth table.
(a) Circuit schematic.
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(b) Circuit symbol.
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\(C\) \(D\) \(Q\) \(\overline{Q}\) Condition
\(0\) \(\times\) \(Q\) \(\overline{Q}\) Hold
\(1\) \(\times\) \(Q\) \(\overline{Q}\) Hold
\(\uparrow\) \(0\) \(0\) \(1\) Reset
\(\uparrow\) \(1\) \(1\) \(0\) Set
(c) tbl-digital-flipflop-D
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Figure 7.7.1. D flip-flop that triggers on the rising edge of the CLK signal. (a) shows the circuit schematic, (b) shows the circuit symbol where the wedge shape on the CLK input distinguishes itself from the symbol for a D latch, and Table 7.7.1(c) shows the truth table for this flip-flop.
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This circuit acts much like the D latch from the previous section except that the outputs are only allowed to change at instants when the CLK signal transitions from LOW to HIGH (Table 7.7.1(c)). The timing diagram in Figure 7.7.2 demonstrates the response of the flip-flop output to a time-varying CLK and \(D\) input signal.
Figure 7.7.2. Timing diagram for the circuit pictured in Figure 7.7.1(a).
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Example 7.7.3. Intermediate stages of rising-edge D flip-flop..

Use the behavior of D latches to show that the circuit in Figure 7.7.2 does indeed produce the timing diagram shown in timing-digital-flipflop-D. To accomplish this, assume \(C\) and \(D\) as shown in the original timing diagram and also assume that \(Q_1=0\) at \(t=0\text{.}\) Produce lines showing the time behavior of \(EN_1\text{,}\) \(Q_1\text{,}\) \(EN_2\text{,}\) and finally \(Q=Q_2\text{.}\) Explain the rationale used to draw each signal.
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Answer.
Figure 7.7.4. Timing diagram for the circuit pictured in Figure 7.7.1(a).
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Solution.
To come.
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Removal of one NOT gate from the flip-flop circuit above produces a D flip-flop that triggers on falling edge of the CLK signal instead of the rising edge. The circuit schematic, circuit symbol, and truth table are shown in Figure 7.7.5.
(a) Circuit schematic.
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(b) Circuit symbol.
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\(C\) \(D\) \(Q\) \(\overline{Q}\) Condition
\(0\) \(\times\) \(Q\) \(\overline{Q}\) Hold
\(1\) \(\times\) \(Q\) \(\overline{Q}\) Hold
\(\downarrow\) \(0\) \(0\) \(1\) Reset
\(\downarrow\) \(1\) \(1\) \(0\) Set
(c) tbl-digital-flipflop-D
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Figure 7.7.5. D flip-flop that triggers on the falling edge of the CLK signal. (a) shows the circuit schematic, (b) shows the circuit symbol where the addition of a bubble on the CLK input indicates the falling-edge response, and Table 7.7.5(c) shows the truth table for this flip-flop.
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